Non-patent document 1 discloses a resistive random access memory apparatus as the conventional nonvolatile memory apparatus. In the resistive random access memory apparatus, a negative pulse (voltage: −2.0V, pulse width: 20 ns) is applied to change a memory cell using TiO2/TiN as a resistance variable element to a low-resistance state (about 200Ω, “1” data), while a positive pulse (voltage: 2.2V, pulse width: 30 ns) is applied to change the memory cell to a high-resistance state (about 80 kΩ, “0” data).
FIG. 16 is a view showing change in a resistance state in the case where positive and negative pulses are applied alternately in the resistive random access memory apparatus disclosed in the non-patent document 1. By applying the positive and negative pulses alternately in this way, the resistance variable element transitions between a high-resistance state HR and a low-resistance state LR substantially stably.
The patent document 1 discloses the conventional resistive random access memory apparatus which attains the operation of the RAM type on premise that the resistance state changes in response to one pulse. In the resistive random access memory apparatus, during writing of data, two kinds of cycles, i.e, a cycle for applying a high-resistance state attaining pulse and a cycle for applying a low-resistance state attaining pulse are executed. To be specific, the high-resistance state attaining pulse is applied once to a cell which is desired to change its resistance state to the high-resistance state and the low-resistance state attaining pulse is applied once to a cell which is desired to change its resistance state to the low-resistance state in a subsequent cycle, so that desired data is written to the cell.
FIG. 17 is a view showing a current-voltage characteristic of the resistance variable element using TMO (transition metal oxide) disclosed in non-patent document 2. As can be seen from the current-voltage characteristic of FIG. 17, the resistive random access memory element using the TMO is capable of transitioning between a high-resistance state and a low-resistance state alternately regardless of whether voltages of different polarities are applied or voltages of the same polarity are applied. Hereinafter, a case where the resistance state of the resistive random access memory element is switched using two kinds of positive voltages will be described. In “SET” in which the high-resistance state is changed to the low-resistance state, a low-resistance state attaining voltage is applied at a first predetermined positive current value using a set current compliance to prevent break of the element due to an increased current, causing the element to transition from the high-resistance state to the low-resistance state. In “RESET” in which the low-resistance state is changed to the high-resistance state, a high-resistance state attaining voltage is applied, so that a second positive current larger than the first positive current flows in the element, causing the element to transition from the low-resistance state to the high-resistance state.
To solve such a problem, in the nonvolatile memory apparatus disclosed in patent document 2, the memory cell is caused to transition to a low-resistance state (delete) prior to writing of data. After deleting the data, a high-resistance state attaining pulse is applied while checking the resistance state of each memory cell, and reading of the resistance state and application of the high-resistance state attaining pulse are repeated until a predetermined high-resistance state is reached. In writing of the data, by applying the high-resistance state attaining pulse while checking the resistance state after the data is deleted once, the application of the high-resistance state attaining pulse to the cell in the high-resistance state does not occur. As a result, the data is not written to a higher resistance level (increased resistance level), and thus there is no write failure in writing from the high-resistance state to the low-resistance state.
In a phase change random access memory apparatus, a minute current flows if a high-resistance state attaining pulse is applied in an amorphous high-resistance state. Due to gradual heating, crystallization occurs. As a result, the resistance value decreases and data breaks. In the phase change random access memory apparatus disclosed in patent document 3, to solve the problem associated with the write operation which would be caused by such an excess current, data to be written to an address is compared to data which has been read in advance from the address and a write pulse is applied when these data do not match.    Non-patent document 1: “High-Speed Resistive Switching of TiO2/TiN Nano-Crystalline Thin Film” Japanese Journal of Applied Physics Vol. 45, No. 11, 2006, pp. L310-L312    Non-patent document 2: “Highly Scalable Non-volatile Resistive Memory using Simple Binary Oxide Driven by Asymmetric Unipolar Voltage Pulses” 0-7803-8684-1/04/$20.00 (c)2004IEEE    Patent document 1: U.S. Pat. No. 7,095,644 Specification    Patent document 2: Japanese Laid-Open Patent Application Publication NO. 2004-185756    Patent document 3: Japanese Laid-Open Patent Application Publication No. 2005-108395